`timescale  1ns / 1ps

module tb_top_module;

// top_module Parameters
parameter PERIOD  = 10;


// top_module Inputs
reg   in1                                  = 0 ;
reg   in2                                  = 0 ;
reg   in3                                  = 0 ;

// top_module Outputs
wire  out                                  ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
end

top_module  u_top_module (
    .in1                     ( in1   ),
    .in2                     ( in2   ),
    .in3                     ( in3   ),

    .out                     ( out   )
);

initial
begin

    $finish;
end

endmodule